1. Field of the Invention
The present invention relates to a packaging process and a package structure, and more particularly to a wafer-level chip packaging process and a chip package structure.
2. Description of Related Art
In the semiconductor production industry, the fabrication of integrated circuits (IC) is mainly divided into three stages: a wafer processing stage, an IC processing stage and an IC packaging stage. To fabricate a silicon chip, a series of steps including wafer fabrication, circuit design, mask making and wafer sawing have to be performed. After the contacts of each chip cut out from a wafer are electrically connected to an external carrier, the chip is encapsulated by using a molding compound. The purpose of packaging the chip is to protect the chip against the effects of moisture, heat and noise and provide a medium of connection between the chip and the external carrier.
However, the conventional IC package is formed by performing a wire bonding process or a flip chip bonding process to electrically connect the contacts on the chips with the corresponding external carriers and then encapsulating each chip with molding compound after the chips are separated in a wafer sawing process. Therefore, before the chip is encapsulated with molding compound, external particles can easily fall on the chip and lower its process yield. Moreover, the foregoing packaging process often incurs a higher cost.
To resolve the above problem, another conventional chip package structure is shown in FIG. 1. The chip package 100 includes a chip 110, a transparent cover panel 120, a spacer 130 and an adhesive layer 140. The chip 110 has a light-sensing area 114 on an active surface 112 and a plurality of pads 116 around the light-sensing area 114. In addition, the adhesive layer 140 encapsulates the spacer 130. Therefore, the transparent cover panel 120 is disposed above the active surface 112 through the support of the spacer 130 and the adhesion of the adhesive layer 140.
However, the adhesive layer 140 of the conventional chip package 100 normally has residual voids or bubbles. Moreover, there is a gap S between the transparent cover panel 120 and the chip 110. If some residual particles are lodged in the gap S during the packaging process, the particles may contaminate or scratch the light-sensing area 114 and cause a change of the path of incident light signals. Consequently, the light-sensing area 114 may receive distorted light signals. As a result, there is a need to improve the structure of the chip package.